Gate stacks for high mobility channel MOS devices need to be developed to match the good characteristics obtained for silicon (Si) channel devices MOS devices used in previous nodes. This, however, has proven difficult. Requirements for providing gate stacks for high mobility channel MOS devices may include: a thin scaled equivalent oxide thickness (EOT), high mobility, low interface defect density (Dit), low gate leakage, and the like. Specifically for high Germanium (Ge) SiGe nMOS devices (e.g. Ge content larger than about 80%) or Ge nMOS devices, it is very difficult to achieve all these requirements.